HD6417706 Datasheet, PDF (13/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Item
Page
10.3 Clock Operating Modes 294
297
Section 11 Watchdog Timer 303
(WDT)
Figure 11.1 Block Diagram of
the WDT
Revision (See Manual for Details)
Description amended
Table 10.2 shows the relationship between the mode control pin
(MD2 to MD0) combinations and the clock operating modes. Table
10.3 shows the usable frequency ranges in the clock operating
modes and frequency ranges of the input clock (crystal oscillation).
Operation cannot be guaranteed if settings other than those listed in
table 10.3 are used.
Caution 4 amended
4. The frequency of the peripheral clock (Pφ):
• The frequency of the peripheral clock (Pφ) is the product of the
frequency of the CKIO pin, the frequency multiplication ratio of
PLL circuit 1, and the division ratio of divider 2.
Figure 11.1 amended
WDT
Standby
cancellation
Internal
reset
request
Interrupt
request
Standby
control
Reset
control
Interrupt
control
Clock selection
Overflow
Divider
Clock selector
Clock
WTCSR
WTCNT
Standby
mode
Peripheral
clock
Bus interface
11.2.1 Watchdog Timer
Counter (WTCNT)
11.2.2 Watchdog Timer
Control/Status Register
(WTCSR)
12.5.2 Status Flag Clear
Timing
Figure 12.9 Status Flag
Clear Timing
13.3.9 Second Alarm
Register (RSECAR)
304 Description amended
… The WTCNT is initialized to H'00 only by a power-on reset through
the RESETP pin. …
304 Description amended
… The WTCSR is initialized to H'00 only by a power-on reset through
the RESETP pin. …
323 Figure 12.9 amended
TCR write cycle
T1
T2
T3
Pφ
Peripheral address bus
TCR address
UNF, ICPF
333 Bit 7 R/W amended
(Before) R → (After) R/W
Rev. 4.00, 03/04, page xiii of xlvi