HD6417706 Datasheet, PDF (258/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

• Single Read
Figure 8.15 shows the timing when a single address read is performed. As the burst length is set to
1 in synchronous DRAM burst read/single write mode, only the required data is output.
Consequently, no unnecessary bus cycles are generated even when a cache-through area is
accessed.
CKIO
Address
upper bits
A12 or A11 *¹
Address
lower bits*²
or
Tr
Tc1
Td1
Tpc
RD/
D31 to D0
Notes: 1. Command bit
2. Column address
Figure 8.15 Basic Timing for Synchronous DRAM Single Read
Rev. 4.00, 03/04, page 212 of 660