HD6417706 Datasheet, PDF (224/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
4
A2W1
1
R/W Area 2 Wait Control
3
A2W0
1
R/W Specify the number of wait states inserted into
physical space area 2.
• For Ordinary memory
Inserted Wait States
WAIT Pin
00:
0
Ignored
01:
1
Enabled
10:
2
Enabled
11:
3
Enabled
• For Synchronus DRAM
Synchronus DRAM :CAS Latency
00:
1
01:
1
10:
2
11:
3
2
A0W2
1
R/W Area 0 Wait Control
1
A0W1
1
0
A0W0
1
R/W Specify the number of wait states inserted into
R/W ^{physical space area 0. Also specify the burst pitch for}
burst transfer.
Refer to table 8.9 for details.
Table 8.6 Area 6 Wait Control
WCR2's bits
Bit 15: Bit 14: Bit 13:
A6W2 A6W1 A6W0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer WAIT Pin
0
Ignored
2
Enable
1
Enable
2
Enable
2
Enable
3
Enable
3
Enable
4
Enable
4
Enable
4
Enable
6
Enable
6
Enable
8
Enable
8
Enable
10
Enable
10
Enable
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