HD6417706 Datasheet, PDF (19/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Item
Figure 24.18 Basic Bus
Cycle (External Wait)
Page Revision (See Manual for Details)
587 Figure 24.18 amended
24.3.6 Synchronous DRAM 599
Timing
Figure 24.30 Synchronous
DRAM Burst Read Bus Cycle
(RAS Down, Same Row
Address, CAS Latency = 1)
24.3.9 H-UDI, AUD Related 619
Pin Timing
Figure 24.57 H-UDI Data
Transfer Timing
D31 to D0
(read)
WEn
(write)
D31 to D0
(write)
t_WED
t_WDD1
t_BSD
t_BSD
BS
t_DAKD1
DACKn
t_WTS t_WTH
WAIT
Figure 24.30 replaced
t_WTS t_WTH
Figure 24.57 amended
TDO
t_TDOD
t_RDS1
t_WED
t_AH
t_RWH
t_WDH3
t_WDH1
t_DAKD2
24.3.11 AC Characteristics 622
Measurement Conditions
B.1 Pin Functions
630
Table B.1 Pin States during
Resets, Power-Down States,
and Bus-Released State
B.3 Processing of Unused 637
Pins
Description amended
I/O signal reference level: VccQ/2 (VccQ = 3.3 ± 0.3 V, Vcc = 1.9
± 0.15 V)
• Input pulse level …
Table B.1 amended
Category
Data bus
Pin
D[15:0]
D[23:16]/PTA[7:0]
D[31:24]/PTB[7:0]
Reset
Power-On Manual
Reset
Reset
Z
I
Z
IP*³
Z
IP*³
Power-Down
Standby Sleep
Z
ZK*³
ZK*³
IO
IOP*³
IOP*³
Bus
Released
Z
ZP*³
ZP*³
Description amended
When EXTAL pin is not used
 EXTAL: Pull up to VccQ or Vss
Rev. 4.00, 03/04, page xix of xlvi