HD6417706 Datasheet, PDF (216/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
13
HIZMEM 0
R/W Hi-Z memory control
Specifies the state of A25 to 0, BS, CS, RD/WR,
WE/DQM, RD, CE2A, CE2B and DRAK0/1 in standby
mode.
0: High-impedance state in standby mode.
1: Driven in standby mode.
12
HIZCNT
0
R/W High-Z Control
Specifies the state of the RAS and the CAS signals at
standby and bus right release.
0: High-impedance state at standby and bus right
release.
11
ENDIAN
0/1*¹
1: Driven at standby and bus right release.
R Endian Flag
Samples the value of the external pin designating
endian upon a power-on reset. Endian for all physical
spaces is decided by this bit, which is read-only.
0: (On reset) Endian setting external pin (MD5) is low.
Indicates the SH7706 is set as big endian.
1: (On reset) Endian setting external pin (MD5) is
high. Indicates the SH7706 is set as little endian.
10
A0BST1
0
R/W Area 0 Burst ROM Control
9
A0BST0
0
R/W Specify whether to use burst ROM in physical space
area 0. When burst ROM is used, set the number of
burst transfers.
00: Access area 0 as ordinary memory
01: Access area 0 as burst ROM (4 consecutive
accesses). Can be used when bus width is 8, 16,
or 32.
10: Access area 0 as burst ROM (8 consecutive
accesses). Can be used when bus width is 8 or
16.
01: Access area 0 as burst ROM (16 consecutive
accesses). Can be used only when bus width is 8.
Rev. 4.00, 03/04, page 170 of 660