HD6417706 Datasheet, PDF (272/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Before mode register setting, a 100 µs idle time (depending on the memory manufacturer) must be
guaranteed after powering on requested by the synchronous DRAM. If the reset signal pulse width
is greater than this idle time, there is no problem in performing mode register setting immediately.
The number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must
be executed. This is usually achieved automatically while various kinds of initialization are being
performed after auto-refresh setting, but a way of carrying this out more dependably is to set a
short refresh request generation interval just while these dummy cycles are being executed. With
simple read or write access, the address counter in the synchronous DRAM used for auto-
refreshing is not initialized, and so the cycle must always be an auto-refresh cycle.
CKIO
A15 to A12
or (A14 to A11)
TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4
A11 (A10)
A12 (A11)
A10 to A2
(A9 to A2)
RD/
or
or
D31 to D0
CKE
(High)
Figure 8.27 Synchronous DRAM Mode Write Timing
Rev. 4.00, 03/04, page 226 of 660