HD6417706 Datasheet, PDF (491/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

16.3.10 FIFO Data Count Set Register 2 (SCFDR2)
The SCFDR2 is a 16-bit register which indicates the number of data stored in the SCFTDR2 and
SCFRDR2. The SCFDR2 is always read from the CPU.
The upper eight bits of this register indicate the number of transmit data items stored in the
SCFTDR2 that have not yet been transmitted. The H'00 means no transmit data, and the H'10
means that the full of transmit data are stored in the SCFTDR2.
The lower eight bits of this register indicate the number of receive data items stored in the
SCFRDR2. The H'00 means no receive data, and the H'10 means that the full of receive data are
stored in the SCFRDR2.
Bit
Bit Name
15 to 13 —
12 to 8 T4 to T0
7 to 5 —
4 to 0 R4 to R0
Initial Value R/W Description
All 0
R Reserved
These bits are always read as 0.
All 0
R Number of non-transmitted data.
All 0
R Reserved
These bits are always read as 0.
All 0
R Number of received data.
16.3.11 SC Port Control Register (SCPCR)
For information about the SC port control register (SCPCR), see section 14.3.8, SC Port Control
Register (SCPCR).
16.3.12 SC Port Data Register (SCPDR)
For information about the SC port data register (SCPDR), see section 14.3.9, SC Port Data
Register (SCPDR).
Rev. 4.00, 03/04, page 445 of 660