HD6417706 Datasheet, PDF (65/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit
Name
Initial Value
R/W
Description
11, 10 
All 0
R
Reserved
These bits always read as 0, and the write
value should always be 0.
9
M

R/W
M bit
8
Q

R/W
Q bit
Used by the DIV0S/U and DIV1 instructions.
7
I3
1
R/W
Interrupt mask bits
6
I2
5
I1
4
I0
1
R/W
4-bit field indicating the interrupt request mask
1
R/W
level.
1
R/W
I3 to I0 do not change to the interrupt
acceptance level when an interrupt is occurred.
3, 2

All 0
R
Reserved
These bits always read as 0, and the write
value should always be 0.
1
S

R/W
S bit
Used by the MAC instruction.
0
T

R/W
T bit
Used by the MOVT, CMP/cond, TAS, TST, BT,
BF, SETT, CLRT, and DT instructions to
indicate true (1) or false (0).
Used by the ADDV/C, SUBV/C, DIV0U/S, DIV1,
NEGC, SHAR/L, SHLR/L, ROTR/L, and
ROTCR/L instructions to indicate a carry,
borrow, overflow, or underflow.
Note: The M, Q, S and T bits can be set or cleared by special instructions in user mode. Their
values are undefined after a reset. All other bits can be read or written in privileged mode.
• Saved Status Register (SSR)
Stores current SR value at time of exception to indicate processor status in return to instruction
stream from exception handler.
Initialized to undefined by a reset.
• Saved Program Counter (SPC)
Stores current PC value at time of exception to indicate return address at completion of
exception handling.
Initialized to undefined by a reset.
Rev. 4.00, 03/04, page 19 of 660