HD6417706 Datasheet, PDF (581/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
2
MSTP5 0
R/W Module Stop 5
Specifies halting of clock supply to the ADC (an
on-chip peripheral module). When the MSTP5 bit
is set to 1, the supply of the clock to the ADC is
halted and all registers are initialized.
0: ADC runs
1: Clock supply to ADC halted and all registers
initialized
1
MSTP4 0
R/W Module Stop 4
Specifies halting the clock supply to the serial
communication interface with FIFO (an on-chip
peripheral module). When the MSTP1 bit is set to
1, the supply of the clock to the SCIF is halted.
0: SCIF runs
1: Clock supply to SCIF halted
0
—
0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
22.3 Operation
22.3.1 Sleep Mode
• Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip supporting
modules continue to run during sleep mode and the clock continues to be output to the CKIO pin.
In sleep mode, the STATUS1 pin is set high and the STATUS0 pin low.
• Canceling Sleep Mode
Sleep mode is canceled by an interrupt (NMI, IRQ, IRL, on-chip supporting module) or reset.
Interrupts are accepted during sleep mode even when the BL bit in the SR register is 1. If
necessary, save SPC and SSR in the stack before executing the SLEEP instruction.
Canceling with an Interrupt: When an NMI, IRQ, IRL or on-chip supporting module interrupt
occurs, sleep mode is canceled and interrupt exception processing is executed. A code indicating
the interrupt source is set in the INTEVT and INTEVT2 registers.
Canceling with a Reset: Sleep mode is canceled by a power-on reset or a manual reset.
Rev. 4.00, 03/04, page 535 of 660