HD6417706 Datasheet, PDF (257/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Figure 8.14 shows the burst read timing when RCD is set to 1, A3W1 and A3W0 are set to 10, and
TPC is set to 1.
The BS cycle, which is asserted for one cycle at the start of a bus cycle for normal space access, is
asserted in each of cycles Td1 to Td4 in a synchronous DRAM cycle. When a burst read is
performed, the address is updated each time CAS is asserted. As the unit of burst transfer is 16
bytes, address updating is performed for A3 and A2 only (A3, A2, and A1 for a 16-bit bus width).
The order of access is as follows: in a fill operation in the event of a cache miss, the missed data is
read first, then 16-byte boundary data including the missed data is read in wraparound mode.
CKIO
Address
upper bits
A12 or A11 *¹
Address
lower bits *²
or
Tr
Trw
Tc1
Tc2 Tc3/Td1 Tc4/Td2 Td3
Td4
Tpc
RD/
D31 to D0
Notes: 1. Command bit
2. Column address
Figure 8.14 Synchronous DRAM Burst Read Wait Specification Timing
Rev. 4.00, 03/04, page 211 of 660