HD6417706 Datasheet, PDF (586/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

22.3.4 Timing of STATUS Pin Changes
The timing of STATUS1 and STATUS0 pin changes is shown in figures 22.2 through 22.9
• Timing for Resets
Power-On Reset:
CKIO
PLL settling
time
STATUS
Normal*²
Reset*¹
0 to 5 Bcyc*³
Notes:
1. Reset:
2. Normal:
3. Bcyc:
HH (STATUS1 high, STATUS0 high)
LL (STATUS1 low, STATUS0 low)
Bus clock cycle
0 to 30 Bcyc*³
Figure 22.2 Power-On Reset STATUS Output
Manual Reset:
Normal*²
CKIO
*¹
STATUS
Normal*³
Reset*²
Normal*³
0 Bcyc or more*⁴
0 to 30 Bcyc*⁴
Notes:
1. During manual reset, STATUS becomes HH (reset) and the internal reset begins after waiting for
the executing bus cycle to end.
2. Reset: HH (STATUS1 high, STATUS0 high)
3. Normal: LL (STATUS1 low, STATUS0 low)
4. Bcyc: Bus clock cycle
Figure 22.3 Manual Reset STATUS Output
Rev. 4.00, 03/04, page 540 of 660