HD6417706 Datasheet, PDF (320/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Even if the priority is set in the fixed mode or in the round-robin mode, it will not give the bus to
the CPU since channel 1 is in the burst mode. This example is illustrated in figure 9.16.
CPU
DMAC
CH1
DMAC
CH1
DMAC
CH0
*¹
DMAC
CH1
*²
DMAC
CH0
*¹
DMAC
CH1
DMAC
CH1
CPU
CPU
DMAC CH1
Burst mode
Round-robin mode in
DMAC CH0 and CH1
DMAC CH1
Burst mode
CPU
Notes: 1. Cycle-steal mode
2. Burst mode
Figure 9.16 Bus State when Multiple Channels are Operating (Priority Level is Round-
robin Mode)
9.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing
Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycles is
controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master.
For details, see section 8, Bus State Controller (BSC).
DREQ Pin Sampling Timing: In the external request mode, the DREQ pin is sampled by clock
pulse (CKIO) falling edge or low level detection. When DREQ input is detected, a DMAC bus
cycle is generated and DMA transfer is performed, at the earliest, three states later.
The second and subsequent DREQ sampling operations are started two cycles after the first
sample.
Rev. 4.00, 03/04, page 274 of 660