HD6417706 Datasheet, PDF (399/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

14.3.5 Serial Mode Register (SCSMR)
The serial mode register (SCSMR) is an eight-bit register that specifies the SCI serial
communication format and selects the clock source for the baud rate generator.
The CPU can always read and write the SCSMR.
Bit
Bit Name Initial Value R/W Description
7
C/A
0
R/W Communication Mode
Selects whether the SCI operates in the
asynchronous or clock synchronous mode.
0: Asynchronous mode
1: Clock synchronous mode
6
CHR
0
R/W Character Length
Selects seven-bit or eight-bit data length in the
asynchronous mode. In the clock synchronous
mode, the data length is always eight bits,
regardless of the CHR setting.
0: Eight-bit data
1: Seven-bit data
Note: When seven-bit data is selected, the MSB
(bit 7) in the SCTDR is not transmitted.
5
PE
0
R/W Parity Enable
Selects whether to add a parity bit to the transmit
data or to check the parity of receive data in
asynchronous mode. In the clock synchronous
mode, a parity bit is neither added nor checked,
regardless of the PE setting.
0: Parity bit not added and not checked
1: Parity bit added and checked
Note: When PE is set to 1, an even or odd parity
bit is added to transmit data, depending on the
parity mode (O/E) setting. Receive data parity is
checked according to the even/odd (O/E) mode
setting.
Rev. 4.00, 03/04, page 353 of 660