HD6417706 Datasheet, PDF (23/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Section 5 Cache................................................................................................. 99
5.1 Feature............................................................................................................................... 99
5.1.1 Cache Structure.................................................................................................... 99
5.2 Register Description.......................................................................................................... 101
5.2.1 Cache Control Register (CCR) ............................................................................ 101
5.2.2 Cache Control Register 2 (CCR2)........................................................................ 102
5.3 Operation........................................................................................................................... 104
5.3.1 Searching the Cache............................................................................................. 104
5.3.2 Read Access ......................................................................................................... 105
5.3.3 Prefetch Operation ............................................................................................... 106
5.3.4 Write Access ........................................................................................................ 106
5.3.5 Write-Back Buffer ............................................................................................... 106
5.3.6 Coherency of Cache and External Memory ......................................................... 107
5.4 Memory-Mapped Cache.................................................................................................... 107
5.4.1 Address Array ...................................................................................................... 107
5.4.2 Data Array............................................................................................................ 108
5.4.3 Usage Examples................................................................................................... 110
Section 6 Interrupt Controller (INTC) .............................................................. 111
6.1 Feature............................................................................................................................... 111
6.2 Input/Output Pin................................................................................................................ 113
6.3 Interrupt Sources ............................................................................................................... 113
6.3.1 NMI Interrupts ..................................................................................................... 113
6.3.2 IRQ Interrupt........................................................................................................ 114
6.3.3 IRL Interrupts....................................................................................................... 115
6.3.4 On-Chip Peripheral Module Interrupts ................................................................ 116
6.3.5 Interrupt Exception Processing and Priority ........................................................ 117
6.4 Register Description.......................................................................................................... 121
6.4.1 Interrupt Priority Registers A to E (IPRA to IPRE)............................................. 121
6.4.2 Interrupt Control Register 0 (ICR0)..................................................................... 122
6.4.3 Interrupt Control Register 1 (ICR1)..................................................................... 123
6.4.4 Interrupt Request Register 0 (IRR0) .................................................................... 125
6.4.5 Interrupt Request Register 1 (IRR1) .................................................................... 127
6.4.6 Interrupt Request Register 2 (IRR2) .................................................................... 128
6.5 Operation........................................................................................................................... 129
6.5.1 Interrupt Sequence ............................................................................................... 129
6.5.2 Multiple Interrupts ............................................................................................... 131
6.6 Interrupt Response Time ................................................................................................... 132
Section 7 User Break Controller ....................................................................... 135
7.1 Feature............................................................................................................................... 135
7.2 Register Description.......................................................................................................... 137
7.2.1 Break Address Register A (BARA) ..................................................................... 137
Rev. 4.00, 03/04, page xxiii of xlvi