HD6417706 Datasheet, PDF (30/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

19.2 Input/Output Pin................................................................................................................ 497
19.3 Register Description.......................................................................................................... 497
19.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 498
19.3.2 A/D Control/Status Register (ADCSR) ............................................................... 499
19.3.3 A/D Control Register (ADCR) ............................................................................ 501
19.4 Bus Master Interface ......................................................................................................... 501
19.5 Access Size of A/D Data Register .................................................................................... 503
19.5.1 Word Access ........................................................................................................ 503
19.5.2 Longword Access ................................................................................................ 503
19.6 Operation .......................................................................................................................... 503
19.6.1 Single Mode (MULTI = 0) .................................................................................. 503
19.6.2 Multi Mode (MULTI = 1, SCN = 0).................................................................... 505
19.6.3 Scan Mode (MULTI = 1, SCN = 1)..................................................................... 506
19.6.4 Input Sampling and A/D Conversion Time ......................................................... 508
19.6.5 External Trigger Input Timing............................................................................. 509
19.7 Interrupt Requests ............................................................................................................. 509
19.8 Definitions of A/D Conversion Accuracy......................................................................... 510
19.9 Usage Note........................................................................................................................ 511
19.9.1 Setting Analog Input Voltage .............................................................................. 511
19.9.2 Processing of Analog Input Pins.......................................................................... 511
19.9.3 Access Size and Read Data.................................................................................. 512
Section 20 D/A Converter (DAC) .....................................................................513
20.1 Feature .............................................................................................................................. 513
20.2 Input/Output Pin................................................................................................................ 514
20.3 Register Description.......................................................................................................... 514
20.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)............................................ 514
20.3.2 D/A Control Register (DACR) ............................................................................ 515
20.4 Operation .......................................................................................................................... 516
Section 21 User Debugging Interface (H-UDI).................................................517
21.1 Feature .............................................................................................................................. 518
21.2 Input/Output Pin................................................................................................................ 518
21.3 Register Description.......................................................................................................... 519
21.3.1 Bypass Register (SDBPR) ................................................................................... 519
21.3.2 Instruction Register (SDIR) ................................................................................. 519
21.3.3 Boundary Scan Register (SDBSR) ...................................................................... 520
21.4 H-UDI Operations............................................................................................................. 525
21.4.1 TAP Controller .................................................................................................... 525
21.4.2 Reset Configuration ............................................................................................. 526
21.4.3 H-UDI Reset ........................................................................................................ 527
21.4.4 H-UDI Interrupt ................................................................................................... 527
21.4.5 Bypass.................................................................................................................. 527
Rev. 4.00, 03/04, page xxx of xlvi