HD6417706 Datasheet, PDF (40/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Figure 24.29 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write × 4),
RCD = 1, TPC = 0, TRWL = 0) ............................................................................. 598
Figure 24.30 Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Same Row Address, CAS Latency = 1)........................................... 599
Figure 24.31 Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Same Row Address, CAS Latency = 2)............................................ 600
Figure 24.32 Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Different Row Address, TPC = 0, RCD = 0, CAS Latency = 1) ...... 601
Figure 24.33 Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Different Row Address, TPC = 1, RCD = 0, CAS Latency = 1) ..... 602
Figure 24.34 Synchronous DRAM Burst Write Bus Cycle
(RAS Down, Same Row Address) ......................................................................... 603
Figure 24.35 Synchronous DRAM Burst Write Bus Cycle
(RAS Down, Different Row Address, TPC = 0, RCD = 0).................................... 604
Figure 24.36 Synchronous DRAM Burst Write Bus Cycle
(RAS Down, Different Row Address, TPC = 1, RCD = 1).................................... 605
Figure 24.37 Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1) ...................... 606
Figure 24.38 Synchronous DRAM Self-Refresh Cycle (TPC = 0)............................................. 606
Figure 24.39 Synchronous DRAM Mode Register Write Cycle ................................................ 607
Figure 24.40 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) .............................. 608
Figure 24.41 PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait).... 609
Figure 24.42 PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait).......... 610
Figure 24.43 PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1,
Two Waits, Burst Pitch = 3)................................................................................... 611
Figure 24.44 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait)....................................... 612
Figure 24.45 PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait) ............ 613
Figure 24.46 PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Wait, Bus Sizing)................. 614
Figure 24.47 TCLK Input Timing .............................................................................................. 616
Figure 24.48 TCLK Clock Input Timing.................................................................................... 616
Figure 24.49 Oscillation Settling Time at RTC Crystal Oscillator Power-on............................. 616
Figure 24.50 SCK Input Clock Timing....................................................................................... 616
Figure 24.51 SCI I/O Timing in Clock Synchronous Mode ....................................................... 617
Figure 24.52 I/O Port Timing ..................................................................................................... 617
Figure 24.53 DREQ Input Timing .............................................................................................. 617
Figure 24.54 DRAK Output Timing........................................................................................... 618
Figure 24.55 TCK Input Timing................................................................................................. 619
Figure 24.56 TRST Input Timing (Reset Hold).......................................................................... 619
Figure 24.57 H-UDI Data Transfer Timing ................................................................................ 619
Figure 24.58 ASEMD0 Input Timing......................................................................................... 620
Figure 24.59 AUD Timing.......................................................................................................... 620
Figure 24.60 External Trigger Input Timing .............................................................................. 621
Figure 24.61 A/D Conversion Timing ........................................................................................ 621
Figure 24.62 Output Load Circuit............................................................................................... 622
Rev. 4.00, 03/04, page xl of xlvi