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HD6417706 Datasheet, PDF (587/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Timing for Canceling Software Standbys
Software Standby to Interrupt:
Oscillation stops
Interrupt request
WDT overflow
CKIO
STATUS
Normal*2
Standby*1
WDT count
Normal*2
Notes: 1. Standby: LH (STATUS1 low, STATUS0 high)
2. Normal: LL (STATUS1 low, STATUS0 low)
Figure 22.4 Software Standby to Interrupt STATUS Output
Software Standby to Power-On Reset:
Oscillation stops
Reset
CKIO
*1
STATUS
Normal*4
Standby*3
*6
Reset*2
Normal*4
Notes:
0 to 10 Bcyc*5
0 to 30 Bcyc*5
1. When software software standby mode is cleared with a power-on reset, the WDT does not count.
Keep
low during the PLL's oscillation settling time.
2. Reset:
HH (STATUS1 high, STATUS0 high)
3. Standby: LH (STATUS1 low, STATUS0 high)
4. Normal: LL (STATUS1 low, STATUS0 low)
5. Bcyc:
Bus clock cycle
6. Undefined
Figure 22.5 Software Standby to Power-On Reset STATUS Output
Rev. 4.00, 03/04, page 541 of 660