HD6417706 Datasheet, PDF (490/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
5
TTRG1 0
R/W Trigger of the Number of Transmit FIFO Data
4
TTRG0 0
R/W Set the reference number of the send data empty.
The TDFE in SCSSR2 is set to 1, when the
transmitting data count has fallen the following trigger
number.
Trigger number of transmit data.
00:
8 (8)
01:
4 (12)
10:
2 (14)
11:
1 (15)
Note: Values in brackets mean the number of empty
bytes in SCFTDR when the TDFE is set.
3
MCE
0
R/W Modem Control Enable
Enables the modem control signals CTS2 and RTS2.
0: Disables the modem signal*
1: Enables the modem signal
Note: * The CTS2 is fixed to active 0 regardless of the
input value, and the RTS2 is also fixed to 0.
2
TFRST 0
R/W Transmit FIFO Data Register Reset
Cancels the transmit data in the SCFTDR2 and resets
the data to the empty state.
0: Disables reset operation*
1: Enables reset operation
Note: * The reset is executed in a hardware reset or
the standby mode.
1
RFRST 0
R/W Receive FIFO Data Register Reset
Cancels the receive data in the SCFRDR2 and resets
the data to the empty state.
0: Disables reset operation*
1: Enables reset operation
Note: * The reset is executed in a hardware reset or
the standby mode.
0
LOOP
0
R/W Loop Back Test
Internally connects the transmit output pin (TXD2) and
receive input pin (RXD2) and enables the loop back
test.
0: Disables the loop back test
1: Enables the loop back test
Rev. 4.00, 03/04, page 444 of 660