HD6417706 Datasheet, PDF (227/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
15
TPC1
0
R/W RAS Precharge Time
14
TPC0
0
R/W When synchronous DRAM interface is selected as
connected memory, they set the minimum number
of cycles until output of the next bank-active
command after precharge.
The number of cycles to be inserted immediately
after issuing a precharge all banks (PALL)
command in auto-refresh or a precharge (PRE)
command in bank-active mode is one cycle less
than the normal value. In bank-active mode,
neither TPC1 nor TPC0 should be cleared to 0.
Normal
Operation
Immediately after* Immediately
Precharge
after
Command
Self-Refresh
00: 1 cycle
0 cycle
2 cycles
01: 2 cycles
1 cycle
5 cycles
10: 3 cycles
2 cycles
8 cycles
11: 4 cycles
3 cycles
11 cycles
Note: * Immediately after a precharge all banks (PALL)
command in auto-refresh and a precharge (PRE)
command in bank-active mode.
13
RCD1
0
R/W RAS-CAS Delay
12
RCD0
0
R/W When synchronous DRAM interface is selected as
connected memory, sets the bank active
read/write command delay time.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
Rev. 4.00, 03/04, page 181 of 660