SH7058 Datasheet, PDF (991/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

25.3.3 Hardware Standby Mode Timing
Figure 25.2 shows sample pin timings for hardware standby mode. A transition to hardware
standby mode is made by driving the HSTBY pin low after driving the RES pin low. Hardware
standby mode is canceled by driving HSTBY high, waiting for clock oscillation to stabilize, then
switching RES from low to high.
Oscillator
pulse
width t_RESW
Oscillation
settling time
+
pulse
width
Reset
exception
processing
Figure 25.2 Hardware Standby Mode Timing
25.4 Software Standby Mode
25.4.1 Transition to Software Standby Mode
To enter software standby mode, set the software standby bit (SSBY) to 1 in SBYCR, then
execute the SLEEP instruction. The SH7058 switches from the program execution state to
software standby mode. In software standby mode, power consumption is greatly reduced by
halting not only the CPU, but the clock and on-chip peripheral modules as well. CPU register
contents and on-chip RAM data are held as long as the prescribed voltages are applied (when the
RAME bit in SYSCR1 is 0). The register contents of some on-chip peripheral modules are
initialized, but some are not. The I/O port state can be selected as held or high impedance by the
port high impedance bit (HIZ) in SBYCR.
25.4.2 Canceling Software Standby Mode
Software standby mode is canceled by an NMI interrupt or a power-on reset.
Cancellation by NMI: Clock oscillation starts when a rising edge or falling edge (selected by the
NMI edge select bit (NMIE) in the interrupt control register (ICR) of the INTC) is detected in the
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