SH7058 Datasheet, PDF (527/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Table 15.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode)
Pφ (MHz)
10
11.0592
12
12.288
14
14.7456
16
17.2032
18
18.432
19.6608
20
External Input Clock (MHz)
2.5000
2.7648
3.0000
3.0720
3.5000
3.6864
4.0000
4.3008
4.5000
4.6080
4.9152
5.0000
Maximum Bit Rate (Bits/s)
156250
172800
187500
192000
218750
230400
250000
268800
281250
288000
307200
312500
Table 15.7 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode)
Pφ (MHz)
10
12
14
16
18
20
External Input Clock (MHz)
1.6667
2.0000
2.3333
2.6667
3.0000
3.3333
Maximum Bit Rate (Bits/s)
1666666.7
2000000.0
2333333.3
2666666.7
3000000.0
3333333.3
15.2.9 Serial Direction Control Register (SDCR)
Bit: 7
6
5
4
3
2
1
0
–
–
–
–
DIR
–
–
–
Initial value: 1
1
1
1
0
0
1
0
R/W: R
R
R
R
R/W
R
R
R
The DIR bit in the serial direction control register (SDCR) selects LSB-first or MSB-first transfer.
With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the
communication mode. With a 7-bit data length, LSB-first transfer must be selected. The
description in this section assumes LSB-first transfer.
Rev. 3.0, 09/04, page 486 of 1086