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SH7058 Datasheet, PDF (1030/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine
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27.3.8 Serial Communication Interface Timing
Table 27.13 shows serial communication interface timing.
Table 27.13 Serial Communication Interface Timing
Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,
PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC,
VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C.
When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1.
When writing or erasing on-chip flash memory, Ta = –40°C to 85°C.
Item
Symbol Min
Max
Unit
Figures
Clock cycle
tscyc
4
—
tcyc
Figure 27.16
Clock cycle (clock sync)
t
6
scyc
—
t
cyc
Clock pulse width
tsckw
0.4
0.6
tscyc
Input clock rise time
tsckr
—
1.5
tcyc
Input clock fall time
tsckf
—
1.5
tcyc
Transmit data delay time
tTxD
—
100
ns
Figure 27.17
Transmit data setup time
tRxS
100
—
ns
Transmit data hold time
tRxH
100
—
ns
SCK0–SCK4
tsckw
VIH
VIH
VIL
tsckr
VIH
VIL
tscyc
tsckf
VIH
VIL
Figure 27.16 SCI Input/Output Timing
Rev. 3.0, 09/04, page 989 of 1086
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