SH7058 Datasheet, PDF (665/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Table 17.2 A/D Converter Registers (cont)
Name
Abbreviation R/W
Initial
Value
Address
Access
Size*¹
A/D data register 27 (H/L)
ADDR27 (H/L) R
H'0000 H'FFFFF846 8, 16
A/D data register 28 (H/L)
ADDR28 (H/L) R
H'0000 H'FFFFF848 8, 16
A/D data register 29 (H/L)
ADDR29 (H/L) R
H'0000 H'FFFFF84A 8, 16
A/D data register 30 (H/L)
ADDR30 (H/L) R
H'0000 H'FFFFF84C 8, 16
A/D data register 31 (H/L)
ADDR31 (H/L) R
H'0000 H'FFFFF84E 8, 16
A/D control/status register 0 ADCSR0
R/(W)*² H'00
H'FFFFF818 8, 16
A/D control register 0
ADCR0
R/W H'0F
H'FFFFF819 8, 16
A/D trigger register 0
A/D control/status register 1
ADTRGR0
ADCSR1
R/W H'FF
R/(W)*² H'00
H'FFFFF76E 8
H'FFFFF838 8, 16
A/D control register 1
ADCR1
R/W H'0F
H'FFFFF839 8, 16
A/D trigger register 1
ADTRGR1
R/W H'FF
H'FFFFF72E 8
A/D control/status register 2 ADCSR2
R/(W)*² H'08
H'FFFFF858 8, 16
A/D control register 2
ADCR2
R/W H'0F
H'FFFFF859 8, 16
A/D trigger register 2
ADTRGR2
R/W H'FF
H'FFFFF72F 8
Notes: Register access with an internal clock multiplication ratio of 4 requires four or five internal
clock (φ) cycles.
1. A 16-bit access must be made on a word boundary.
2. Only 0 can be written to bit 7 to clear the flag.
Rev. 3.0, 09/04, page 624 of 1086