SH7058 Datasheet, PDF (740/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

19.2.5 Test Reset (TRST)
The test reset pin (TRST) initializes the H-UDI asynchronously. If no signal is input, TRST is
fixed at 1 by internal pull-up.
19.3 Register Descriptions
19.3.1 Instruction Register (SDIR)
Bit: 15
14
13
12
11
10
9
8
TS3 TS2 TS1 TS0
—
—
—
—
Initial value: 1
1
1
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. H-UDI
instructions can be transferred to SDIR by serial input from TDI. SDIR can be initialized by the
TRST signal, but is not initialized by a reset or in software standby mode.
SDIR defines four valid bits for instruction. If an instruction exceeding four bits is input, the last
four bits of the serial data will be stored in SDIR.
Operation is not guaranteed if a reserved instruction is set in this register.
Bits 15 to 12—Test Set Bits (TS3–TS0): Table 19.4 shows the instruction configuration.
Rev. 3.0, 09/04, page 699 of 1086