SH7058 Datasheet, PDF (620/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

16.5.8 Unread Message Status Register n (UMSR1n, UMSR0n) (n = 0, 1)
UMSR1 and UMSR0 are 16-bit readable/writable registers that record the receive mailboxes
whose contents have not been accessed by the host CPU prior to a new message being received. If
the host CPU has not cleared the corresponding bit in RXPR/RFPR when a new message for a
mailbox is received, the corresponding UMSR bit is set. This bit is cleared by writing 1. Writing 0
is ignored.
If a mailbox is set for transmission, the corresponding UMSR bit cannot be set.
• UMSR1n (n = 0, 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UMSR1[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/
WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1
Bit
Bit Name
15 to 0 UMSR1[15:0]
Initial Value
0
R/W
R/WC1
Description
Indicate that an unread message has been
overwritten/overrun for mailboxes 31 to 16.
0: Clearing condition: Writing 1
1: Unread message is overwritten by a new
message or overrun
Setting Condition: When a new message is
received before RXPR/RFPR is cleared.
Rev. 3.0, 09/04, page 579 of 1086