SH7058 Datasheet, PDF (778/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

AUDCK
AUDATAn
0000 1110 A3–A0
DIR
Input/output switchover
A31–A28 D3–D0
D31–D28
0000
Not ready
Input
0001
Ready
Output
0001 0001
Ready Ready
Figure 20.6 Example of Write Operation (Longword Write)
AUDCK
AUDATAn
0000 1010 A3–A0
DIR
Input
Input/output switchover
A31–A28
0000
Not ready
0101
Ready
(Bus error)
0101 0101
Ready Ready
(Bus error) (Bus error)
Output
Figure 20.7 Example of Error Occurrence (Longword Read)
20.5 Usage Notes
20.5.1 Initialization
The debugger’s internal buffers and processing states are initialized in the following cases:
1. In a power-on reset
2. In hardware standby mode
3. When AUDRST is driven low
4. When the AUDSRST bit is set to 1 in the SYSCR1 register (see section 25.2.2)
5. When the MSTOP3 bit is set to 1 in the SYSCR2 register (see section 25.2.3)
20.5.2 Operation in Software Standby Mode
The debugger is not initialized in software standby mode. However, since the SH7058’s internal
operation halts in software standby mode:
1. When AUDMD is high (RAM monitor mode): Operation stops. This setting should not be
used in standby mode.
2. When AUDMD is low (PC trace): Operation stops. However, operation continues when
software standby is released.
Rev. 3.0, 09/04, page 737 of 1086