SH7058 Datasheet, PDF (316/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Timer Status Registers 6 and 7 (TSR6, TSR7)
TSR6 and TRS7 indicate the channel 6 and 7 free-running counter up-count and down-count
status, and cycle register compare status.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
7
UDxD
0
R
6
UDxC
0
R
5
UDxB
0
R
Note: * Only 0 can be written to clear the flag.
x = 6 or 7
4
UDxA
0
R
3
2
1
0
CMFxD CMFxC CMFxB CMFxA
0
0
0
0
R/(W)* R/(W)* R/(W)* R/(W)*
UDxA to UDxD relate to TSR6 only. Bits relating to TSR7 always read 0.
• Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 7—Count-Up/Count-Down Flag 6D (UD6D): Status flag that indicates the TCNT6D count
operation.
Bit 7: UD6D
0
1
Description
Free-running counter TCNT6D operates as an up-counter
Free-running counter TCNT6D operates as a down-counter
• Bit 6—Count-Up/Count-Down Flag 6C (UD6C): Status flag that indicates the TCNT6C count
operation.
Bit 6: UD6C
0
1
Description
Free-running counter TCNT6C operates as an up-counter
Free-running counter TCNT6C operates as a down-counter
Rev. 3.0, 09/04, page 275 of 1086