SH7058 Datasheet, PDF (587/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
4
MCR4
0
R/W CAN Endian Mode
Controls whether the HCAN should transmit the
messages in little endian mode or big endian
mode. By using this bit, in other words, it is
possible to set different endian mode to the HCAN
and the external network. Note that this bit is only
valid when data field is transmitted/received.
0: Data field transmitted/received in big endian
mode
1: Data field transmitted/received in little endian
mode
3
MCR3
0
R/W Reserved
The initial value should be retained.
2
MCR2
0
R/W Message Transmission Priority
Selects the order of transmission for pending
transmit data.
When this bit is set, pending transmit data are
sent in order of the bit position in the transmit wait
register (TXPR). The order of transmission starts
from mailbox 31 as the highest priority, and then
down to mailbox 1 (if those mailboxes are
configured for transmission).
Important: This function cannot be used for timer
triggered transmission.
When this bit is cleared, all messages for
transmission are queued with respect to their
priority (by running internal arbitration). The
highest priority message has the arbitration field
with the lowest digital value and is transmitted
first. The internal arbitration includes the RTR bit
and the IDE bit.
0: Transmission order determined by message ID
priority
1: Transmission order determined by mailbox
number priority (mailbox 31 → mailbox 1)
Rev. 3.0, 09/04, page 546 of 1086