SH7058 Datasheet, PDF (896/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Note that the CPU must not branch to an area without the execution code and get out of control.
The on-chip program download area and stack area must not be overwritten. If CPU runaway
occurs or the download area or stack area is overwritten, the value of flash memory cannot be
guaranteed.
The download of the on-chip program, initialization, initiation of the programming/erasing
program must not be executed in the processing of the user branch destination. Programming or
erasing cannot be guaranteed when returning from the user branch destination. The program data
which has already been prepared must not be programmed.
Store general registers R8 to R15 and the control register GBR. General registers R0 to R7 are
available without storing them.
Moreover, the programming/erasing interface registers must not be written to or RAM emulation
mode must not be entered in the processing of the user branch destination.
After the processing of the user branch has ended, the programming/erasing program must be
returned to by using the RTS instruction.
For the execution intervals of the user branch processing, see note 2 (User branch processing
intervals) in section 23.8.3, Other Notes.
(2.3) Flash pass/fail result parameter (FPFR: general register R0 of CPU)
This parameter indicates the return value of the initialization result.
Bit :
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit :
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Bit :
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
Bit :
7
6
5
4
3
2
1
0
0
0
0
0
0
BR
FQ
SF
• Bits 31 to 3—Unused: Return 0.
• Bit 2—User Branch Error Detect (BR): Returns the check result whether the specified user
branch destination address is in the area other than the storage area of the programming/erasing
program which has been downloaded .
Rev. 3.0, 09/04, page 855 of 1086