SH7058 Datasheet, PDF (294/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bits 6 to 4—I/O Control 3B2 to 3B0, 4B2 to 4B0, 5B2 to 5B0, 3D2 to 3D0, 4D2 to 4D0, 5D2
to 5D0 (IO3B2 to IO3B0, IO4B2 to IO4B0, IO5B2 to IO5B0, IO3D2 to IO3D0, IO4D2 to
IO4D0, IO5D2 to IO5D0): These bits select the general register (GR) function.
Bit 6:
IOxx2
0
1
Bit 5:
IOxx1
0
1
0
1
Bit 4:
IOxx0
0
1
0
1
0
1
0
1
xx = 3B, 4B, 5B, 3D, 4D, or 5D
Description
GR is an output
compare register
GR is an input
capture register
(input capture by
channel 3 and 9
compare-match
enabled)
Compare-match disabled; pin output
undefined
(Initial value)
0 output on GR compare-match
1 output on GR compare-match
Toggle output on GR compare-match
Input capture disabled (In channel 3
only, GR cannot be written to)
Input capture in GR on rising edge at
TIOxx pin (GR cannot be written to)
Input capture in GR on falling edge at
TIOxx pin (GR cannot be written to)
Input capture in GR on both rising and
falling edges at TIOxx pin (GR cannot be
written to)
• Bit 3—Clear Counter Enable Flag 3A, 4A, 5A, 3C, 4C, 5C (CCI3A, CCI4A, CCI5A, CCI3C,
CCI4C, CCI5C): These bits select enabling or disabling of free-running counter (TCNT)
clearing.
Bit 3: CCIxx
Description
0
TCNT clearing disabled
1
TCNT cleared on GR compare-match
xx = 3A, 4A, 5A, 3C, 4C, or 5C
(Initial value)
TCNT is cleared on compare-match only when GR is functioning as an output compare
register.
Rev. 3.0, 09/04, page 253 of 1086