SH7058 Datasheet, PDF (289/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bits 2 to 0—I/O Control 1A2 to 1A0, 1C2 to 1C0, 1E2 to 1E0, 1G2 to 1G0 (IO1A2 to IO1A0,
IO1C2 to IO1C0, IO1E2 to IO1E0, IO1G2 to IO1G0): These bits select the general register
(GR) function.
Bit 2:
IO1x2
0
Bit 1:
IO1x1
0
1
1
0
1
x = A, C, E, or G
Bit 0:
IO1x0
0
1
0
1
0
1
0
1
Description
GR is an output
compare register
GR is an input
capture register
Compare-match disabled; pin output
undefined
(Initial value)
0 output on GR compare-match
1 output on GR compare-match
Toggle output on GR compare-match
Input capture disabled
Input capture in GR on rising edge at
TIO1x pin (GR cannot be written to)
Input capture in GR on falling edge at
TIO1x pin (GR cannot be written to)
Input capture in GR on both rising and
falling edges at TIO1x pin (GR cannot be
written to)
Rev. 3.0, 09/04, page 248 of 1086