SH7058 Datasheet, PDF (588/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
1
MCR1
0
R/W Halt Request
Setting this bit causes the CAN controller to
complete its current operation and then to cut off
the CAN bus. The HCAN remains in halt mode
until this bit is cleared. During halt mode, the CAN
interface does not join the CAN bus activity or
does not store messages nor transmit messages.
All of the registers and mailbox contents are
retained. The HCAN will complete the current
operation if it is a transmitter or a receiver, and
then enter halt mode. If the CAN bus is in the idle
or intermission state, the HCAN will enter halt
mode immediately. Entering halt mode is notified
by IRR0 and GSR4. If a halt request is made
during bus off, the HCAN-II remains bus off even
after 128 × 11 recessive bits. In order to exit this
state, the halt state needs to be canceled by
software.
In halt mode, the HCAN configuration can be
modified as it does not join the bus activity. This
bit has to be cleared to 0 to re-join the CAN bus.
After this bit is cleared, the CAN interface waits
until it detects 11 recessive bits, and then joins
the CAN bus.
0: Normal operating mode
1: Halt mode transition request
Rev. 3.0, 09/04, page 547 of 1086