SH7058 Datasheet, PDF (866/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Table 22.18 Port J Data Register (PJDR) Read/Write Operations
Bits 15 to 0:
PJIOR
Pin Function
0
General input
Read
Pin state
Other than
general input
Pin state
1
General output PJDR value
Other than
PJDR value
general output
Write
Value is written to PJDR, but does not affect pin
state
Value is written to PJDR, but does not affect pin
state
Write value is output from pin
Value is written to PJDR, but does not affect pin
state
22.10.3 Port J Port Register (PJPR)
Bit: 15
14
13
12
11
10
9
PJ15PR PJ14PR PJ13PR PJ12PR PJ11PR PJ10PR PJ9PR
Initial value: PJ15 PJ14 PJ13 PJ12 PJ11 PJ10 PJ9
R/W: R
R
R
R
R
R
R
8
PJ8PR
PJ8
R
Bit:
Initial value:
R/W:
7
PJ7PR
PJ7
R
6
PJ6PR
PJ6
R
5
PJ5PR
PJ5
R
4
PJ4PR
PJ4
R
3
PJ3PR
PJ3
R
2
PJ2PR
PJ2
R
1
PJ1PR
PJ1
R
0
PJ0PR
PJ0
R
The port J port register (PJPR) is a 16-bit read-only register that always stores the value of the
port J pins. The CPU cannot write data to this register. Bits PJ15PR to PJ0PR correspond to pins
PJ15/TI9F to PJ0/TIO2A. If PJPR is read, the corresponding pin values are returned.
Rev. 3.0, 09/04, page 825 of 1086