SH7058 Datasheet, PDF (600/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
6
IRR6
0
R/W Bus Off/Bus Off Recover Interrupt Flag
This bit is set when the HCAN enters the bus-off
state or when the HCAN leaves bus-off and
returns to error-active. This is because the
existing condition that 11 recessive bits have
received 128 times when TEC ≥ 256 at the node
or in the bus-off state. This bit remains latched
even when the HCAN node cancels the bus-off
state, and needs to be cleared by software. GSR0
should be read to determine whether the HCAN
has become bus-off or error active. This bit is
cleared by writing 1 even if the HCAN is still in the
bus-off state. Writing 0 is ignored.
0: Clearing condition: Writing 1
1: Bus off state caused by transmit error or error
active state returning from bus-off
Setting condition: When 11 recessive bits have
received 128 times when TEC ≥ 256 at the
node or in the bus-off state
5
IRR5
0
R/W Error Passive Interrupt Flag
Indicates that the error passive state caused by
the transmit or receive error counter. This bit is
cleared by writing 1. Writing 0 is ignored. If this bit
is cleared, the node may still be error passive.
0: Clearing condition: Writing 1
1: Error passive state caused by transmit/receive
error
Setting condition: When TEC ≥ 128 or REC ≥
128
4
IRR4
0
R/W Receive Overload Warning Interrupt Flag
This bit is set and latched if the receive error
counter (REC) reaches a value greater than 96.
This bit is cleared by writing 1. Writing 0 is
ignored. When the interrupt is cleared, REC still
holds its value greater than 96.
0: Clearing condition: Writing 1
1: Error warning state caused by receive error
Setting condition: When REC ≥ 96
Rev. 3.0, 09/04, page 559 of 1086