SH7058 Datasheet, PDF (87/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Table 2.10 Classification of Instructions (cont)
Operation
Classification Types Code
System
control
11 CLRT
CLRMAC
LDC
LDS
NOP
RTE
SETT
SLEEP
STC
STS
TRAPA
Floating-point 15
instructions
FABS
FADD
FCMP
FDIV
FLDI0
FLDI1
FLDS
FLOAT
FMAC
FMOV
FMUL
FNEG
FSTS
FSUB
FTRC
FPU-related 2
LDS
CPU
STS
instructions
Total: 79
Function
No. of
Instructions
T bit clear
31
MAC register clear
Load to control register
Load to system register
No operation
Return from exception processing
T bit set
Transition to power-down mode
Store control register data
Store system register data
Trap exception handling
Floating-point absolute value
22
Floating-point addition
Floating-point comparison
Floating-point division
Floating-point load immediate 0
Floating-point load immediate 1
Floating-point load into system register FPUL
Integer-to-floating-point conversion
Floating-point multiply-and-accumulate
operation
Floating-point data transfer
Floating-point multiplication
Floating-point sign inversion
Floating-point store from system register
FPUL
Floating-point subtraction
Floating-point conversion with rounding to
integer
Load into floating-point system register
8
Store from floating-point system register
172
Rev. 3.0, 09/04, page 46 of 1086