SH7058 Datasheet, PDF (899/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

(3.3) Flash pass/fail parameter (FPFR: general register R0 of CPU)
This parameter indicates the return value of the program processing result.
Bit :
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit :
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Bit :
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
Bit :
7
6
5
4
3
2
1
0
0
MD
EE
FK
0
WD
WA
SF
• Bits 31 to 7—Unused: Return 0.
• Bit 6—Programming Mode Related Setting Error Detect (MD): Returns the check result of
whether the signal input to the FWE pin is high and whether the error protection state is
entered.
When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is
written to this bit. The input level to the FWE pin and the error protection state can be confirmed
with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter
the error protection state, see section 23.6.3, Error Protection.
Bit 6
MD
0
1
Description
FWE and FLER settings are normal (FWE = 1, FLER = 0)
FWE = 0 or FLER = 1, and programming cannot be performed
• Bit 5—Programming Execution Error Detect (EE): 1 is returned to this bit when the specified
data could not be written because the user MAT was not erased or when flash-memory related
register settings are partially changed on returning from the user branch processing.
If this bit is set to 1, there is a high possibility that the user MAT is partially rewritten. In this case,
after removing the error factor, erase the user MAT.
If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when programming
is performed. In this case, both the user MAT and user boot MAT are not rewritten.
Programming of the user boot MAT must be executed in boot mode or programmer mode.
Rev. 3.0, 09/04, page 858 of 1086