SH7058 Datasheet, PDF (571/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Register Name
MBx[4], MBx[5]*
Address
Bit
H'104 + N×32 15
14
Bit Name
CCM
TTE
Description
CAN-ID Compare Match
When this bit is set, message reception
in the corresponding mailbox can
generate two triggers.
If TCR9 is set to 1, TCR14 is cleared to
freeze ICR0. If TCR10 is set to 1,
TCNTR (timer counter register) is
automatically cleared and the LOSR
(local offset register) value is set.
Important: This function is not supported
by the SH7058.
Thus the write value should be 0.
Time Trigger Enable
When this bit is set, a mailbox in which
TXPR has been already set transmits a
message at a time set in the Tx trigger
time field.
Important: If this bit is set, a failure
occurs during message transmission.
Therefore setting is prohibited. The write
value should be 0. The value read as the
initial value is not guaranteed.
Rev. 3.0, 09/04, page 530 of 1086