SH7058 Datasheet, PDF (982/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Section 24 RAM
24.1 Overview
The SH7058 has 48 kbytes of on-chip RAM. The on-chip RAM is linked to the CPU, direct
memory access controller (DMAC), and advanced user debugger (AUD) with a 32-bit data bus
(figure 24.1).
The CPU, DMAC, and AUD can access data in the on-chip RAM in 8, 16, or 32 bit widths. On-
chip RAM data can always be accessed in one cycle for a read and two states for a write, making
the RAM ideal for use as a program area, stack area, or data area, which require high-speed
access. The contents of the on-chip RAM are held in both the sleep and software standby modes.
When the RAME bit (see below) is cleared to 0, the on-chip RAM contents are also held in
hardware standby mode.
The on-chip RAM is allocated to addresses H'FFFF0000 to H'FFFFBFFF.
SH7058
8
bits
H'FFFF0000
H'FFFF0004
Internal data bus (32 bits)
8
8
bits
bits
H'FFFF0001
H'FFFF0005
H'FFFF0002
H'FFFF0006
8
bits
H'FFFF0003
H'FFFF0007
On-chip RAM
H'FFFFBFFC H'FFFFBFFD H'FFFFBFFE H'FFFFBFFF
Figure 24.1 Block Diagram of RAM
Rev. 3.0, 09/04, page 941 of 1086