SH7058 Datasheet, PDF (27/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Section 8 User Break Controller (UBC)............................................................125
8.1 Overview........................................................................................................................... 125
8.1.1 Features................................................................................................................ 125
8.1.2 Block Diagram ..................................................................................................... 126
8.1.3 Register Configuration......................................................................................... 127
8.2 Register Descriptions ........................................................................................................ 127
8.2.1 User Break Address Register (UBAR) ................................................................ 127
8.2.2 User Break Address Mask Register (UBAMR) ................................................... 128
8.2.3 User Break Bus Cycle Register (UBBR) ............................................................. 130
8.2.4 User Break Control Register (UBCR).................................................................. 132
8.3 Operation .......................................................................................................................... 133
8.3.1 Flow of the User Break Operation ....................................................................... 133
8.3.2 Break on On-Chip Memory Instruction Fetch Cycle ........................................... 135
8.3.3 Program Counter (PC) Values Saved................................................................... 135
8.4 Examples of Use ............................................................................................................... 135
8.4.1 Break on CPU Instruction Fetch Cycle................................................................ 135
8.4.2 Break on CPU Data Access Cycle ....................................................................... 136
8.4.3 Break on DMA Cycle .......................................................................................... 137
8.5 Usage Notes ...................................................................................................................... 138
8.5.1 Simultaneous Fetching of Two Instructions ........................................................ 138
8.5.2 Instruction Fetches at Branches ........................................................................... 138
8.5.3 Contention between User Break and Exception Processing ................................ 139
8.5.4 Break at Non-Delay Branch Instruction Jump Destination.................................. 139
8.5.5 User Break Trigger Output .................................................................................. 139
8.5.6 Module Standby ................................................................................................... 140
8.5.7 Internal Clock (φ) Multiplication Ratio and UBCTRG Pulse Width ................... 140
Section 9 Bus State Controller (BSC) ...............................................................141
9.1 Overview........................................................................................................................... 141
9.1.1 Features................................................................................................................ 141
9.1.2 Block Diagram ..................................................................................................... 142
9.1.3 Pin Configuration................................................................................................. 143
9.1.4 Register Configuration......................................................................................... 143
9.1.5 Address Map ........................................................................................................ 144
9.2 Description of Registers.................................................................................................... 146
9.2.1 Bus Control Register 1 (BCR1) ........................................................................... 146
9.2.2 Bus Control Register 2 (BCR2) ........................................................................... 148
9.2.3 Wait Control Register (WCR).............................................................................. 151
9.2.4 RAM Emulation Register (RAMER)................................................................... 152
9.3 Accessing External Space ................................................................................................. 154
9.3.1 Basic Timing........................................................................................................ 154
9.3.2 Wait State Control................................................................................................ 155
9.3.3 CS Assert Period Extension ................................................................................. 157
Rev. 3.0, 09/04, page xxiv of xxxviii