SH7058 Datasheet, PDF (407/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

16-bit correction counter 10F (TCNT10F) has Pφ as its input and is constantly compared with
16-bit correction counter 10E (TCNT10E). When the 16-bit correction counter 10F
(TCNT10F) value is smaller than that in 16-bit correction counter 10E (TCNT10E), it is
incremented and generates count-up AGCKM. When the 16-bit correction counter 10F
(TCNT10F) value exceeds that in 16-bit correction counter 10E (TCNT10E), no count-up
operation is performed. The TI10 multiplied signal (AGCKM) generated when TCNT10F is
incremented is output to the channel 1 to 5 free-running counters (TCNT1A, TCNT1B,
TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5), and an up-count can be performed on
AGCKM by setting this as the counter clock on each channel. TCNT10F is constantly
compared with the 16-bit correction counter clear register (TCCLR10), and when the free-
running counter 10F (TCNT10F) and correction counter clear register (TCCLR10) values
match, the TCNT10F up-count stops. Setting TRG1AEN, TRG1BEN, TRG2AEN, and
TRG2BEN in the timer control register (TCR10) enables the channel 1 and 2 free-running
counters (TCNT1A, TCNT1B, TCNT2A, TCNT2B) to be cleared at this time. If TI10 is input
when TCNT10D = H'0000, initialization and correction operations are performed. When
TCNT10F = TCCLR10, TCNT10F is cleared to H'0001. When TCNT10F ≠ TCCLR10,
TCNT10F automatically counts up to the TCCLR10 value, and is cleared to H'0001.
Channel 11: Channel 11 has a 16-bit free-running counter (TCNT11) and two 16-bit general
registers (GR11A and GR11B). TCNT11 is an up-counter that performs free-running operation.
The counter can generate an interrupt request when it overflows. The two general registers
(GR11A and GR11B) each have a corresponding external signal I/O pin (TIO11A, TIO11B), and
can be used as input capture or output compare registers.
When used for input capture, the free-running counter (TCNT11) value is captured by means of
input from the corresponding external signal I/O pin (TIO11A, TIO11B). Rising edge, falling
edge, or both edges can be selected for the input capture signal in the timer I/O control register
(TIOR11). When used for output compare, compare-match with the free-running counter
(TCNT11) is performed. For the output from the external signal I/O pins by compare-match, 0
output, 1 output, or toggle output can be selected in the timer I/O control register (TIOR11). An
interrupt can be requested on the occurrence of the respective input capture or compare-match.
When the two general registers (GR11A and GR11B) are designated for compare-match use, a
compare-match signal can be output to the APC.
Prescaler: The ATU-II has a dedicated prescaler with a 2-stage configuration. The first stage
comprises 5-bit prescalers (PSCR1 to PSCR4) that generate a 1/m clock (where m = 1 to 32) with
respect to clock Pφ. The second prescaler stage allows selection of a clock obtained by further
scaling the clock from the first stage by 2n (where n = 0 to 5) according to the timer control
registers for the respective channels (TCR1A, TCR1B, TCR2A, TCR2B, TCR3 to TCR5, TCR6A,
TCR6B, TCR7A, TCR7B, TCR8, TCR11).
The prescalers of channels 1 to 8 and 11 have a 2-stage configuration, while the channel 0 and 10
prescalers only have a first stage. The first-stage prescaler is common to channels 0 to 5, 8, and
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