SH7058 Datasheet, PDF (292/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bits 2 to 0—I/O Control 2A2 to 2A0, 2C2 to 2C0, 2E2 to 2E0, 2G2 to 2G0 (IO2A2 to IO2A0,
IO2C2 to IO2C0, IO2E2 to IO2E0, IO2G2 to IO2G0): These bits select the general register
(GR) function.
Bit 2:
IO2x2
0
Bit 1:
IO2x1
0
1
1
0
1
x = A, C, E, or G
Bit 0:
IO2x0
0
1
0
1
0
1
0
1
Description
GR is an output
compare register
GR is an input
capture register
Compare-match disabled; pin output
undefined
(Initial value)
0 output on GR compare-match
1 output on GR compare-match
Toggle output on GR compare-match
Input capture disabled
Input capture in GR on rising edge at
TIO2x pin (GR cannot be written to)
Input capture in GR on falling edge at
TIO2x pin (GR cannot be written to)
Input capture in GR on both rising and
falling edges at TIO2x pin (GR cannot be
written to)
Rev. 3.0, 09/04, page 251 of 1086