SH7058 Datasheet, PDF (219/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Figure 10.2 is a flowchart of this procedure.
Start
Initial settings
(SAR, DAR, DMATCR, CHCR,
DMAOR)
DE, DME = 1 and
No
NMIF, AE, TE = 0?
Yes
Transfer request
No
occurs?*¹
Yes
Transfer (1 transfer unit);
DMATCR – 1 → DMATCR, SAR, and DAR
updated
*²
*³
Bus mode
No
DMATCR = 0?
Yes
DEI interrupt request (when IE = 1)
Does
NMIF = 1, AE = 1,
No
DE = 0, or DME
= 0?
Yes
Transfer ends
Does
NMIF = 1, AE = 1,
No
DE = 0, or DME
= 0?
Yes
Transfer aborted
Normal end
Notes: 1. In auto-request mode, transfer begins when NMIF, AE, and TE are all 0,
and the DE and DME bits are set to 1.
2. Cycle-steal mode
3. Burst mode
Figure 10.2 DMAC Transfer Flowchart
Rev. 3.0, 09/04, page 178 of 1086