SH7058 Datasheet, PDF (298/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Timer Status Register 0 (TSR0)
TSR0 indicates the status of channel 0 interval interrupts, input capture, and overflow.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
7
IIF2B
0
R/(W)*
6
IIF2A
0
R/(W)*
5
IIF1
0
R/(W)*
4
OVF0
0
R/(W)*
3
ICF0D
0
R/(W)*
2
ICF0C
0
R/(W)*
1
ICF0B
0
R/(W)*
0
ICF0A
0
R/(W)*
Note: * Only 0 can be written to clear the flag.
• Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 7—Interval Interrupt Flag 2B (IIF2B): Status flag that indicates the generation of an
interval interrupt.
Bit 7: IIF2B
0
1
Description
[Clearing condition]
When IIF2B is read while set to 1, then 0 is written to IIF2B
[Setting condition]
When interval interrupt selected by ITVRR2B is generated
(Initial value)
• Bit 6—Interval Interrupt Flag 2A (IIF2A): Status flag that indicates the generation of an
interval interrupt.
Bit 6: IIF2A
0
1
Description
[Clearing condition]
When IIF2A is read while set to 1, then 0 is written to IIF2A
[Setting condition]
When interval interrupt selected by ITVRR2A is generated
(Initial value)
Rev. 3.0, 09/04, page 257 of 1086