SH7058 Datasheet, PDF (451/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Sample Setup Procedure for Channel 3 Input Capture Triggered by Channel 9 Compare-
Match: An example of the setup procedure for compare-match signal transmission is shown in
figure 11.62.
Start
Set port-ATU-II commection 1 _{1. Set the port control register, corresponding to the port for}
signal input to the event counter, to ATU event counter input.
2. Set the channel 3 timer I/O control register (TIOR3A,
Set input capture
TIOR3B), and select the input capture disable setting for the
2 _{general registers (GR3A to GR3D). Input from pins TIO3A to}
TIO3D is masked.
3. Select the event counter count edge with the EGSEL bits in
Select compare-match 3
the channel 9 timer control register (TCR9A, TCR9B), and
set the TRG3xEN bit to 1. Set the timing for capture in the
general register (GR9A to GR9D).
4. Set bit STR3 to 1 in the timer start register (TSTR) to start
Start counter
4 ^{the channel 3 free-running counter (TCNT3).}
5. Input a signal to the event counter input pin.
Start event input
Input capture operation
Note: An interrupt request can be sent to the CPU upon
5
channel 9 compare-match by making a setting in the
timer interrupt enable register (TIER), but an interrupt
request cannot be sent to the CPU upon channel 3 input
capture.
Figure 11.62 Sample Setup Procedure for Compare-Match Signal Transmission
Rev. 3.0, 09/04, page 410 of 1086