SH7058 Datasheet, PDF (287/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Timer I/O Control Registers 1A to 1D (TIOR1A to TIOR1D)
TIOR1A
Bit: 7
6
5
4
3
2
1
0
— IO1B2 IO1B1 IO1B0 — IO1A2 IO1A1 IO1A0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W
R
R/W R/W R/W
TIOR1B
Bit: 7
6
5
4
3
2
1
0
— IO1D2 IO1D1 IO1D0 — IO1C2 IO1C1 IO1C0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W
R
R/W R/W R/W
TIOR1C
Bit: 7
6
5
4
3
2
1
0
— IO1F2 IO1F1 IO1F0 — IO1E2 IO1E1 IO1E0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W
R
R/W R/W R/W
TIOR1D
Bit: 7
6
5
4
3
2
1
0
— IO1H2 IO1H1 IO1H0 — IO1G2 IO1G1 IO1G0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W
R
R/W R/W R/W
Registers TIOR1A to TIOR1D specify whether general registers GR1A to GR1H are used as input
capture or compare-match registers, and also perform edge detection and output value setting.
Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
• Bit 7—Reserved: This bit is always read as 0. The write value should always be 0.
Rev. 3.0, 09/04, page 246 of 1086