SH7058 Datasheet, PDF (852/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

22.5.2 Port D Data Register (PDDR)
Bit: 15
—
Initial value: 0
R/W: R
14
13
12
11
10
9
8
—
PD13 PD12 PD11 PD10 PD9 PD8
DR
DR
DR
DR
DR
DR
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
DR
DR
DR
DR
DR
DR
DR
DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The port D data register (PDDR) is a 16-bit readable/writable register that stores port D data.
Bits PD13DR to PD0DR correspond to pins PD13/PULS6/HTxD0/HTxD1 to PD0/TIO1A.
When a pin functions as a general output, if a value is written to PDDR, that value is output
directly from the pin, and if PDDR is read, the register value is returned directly regardless of
the pin state.
When a pin functions as a general input, if PDDR is read, the pin state, not the register value, is
returned directly. If a value is written to PDDR, although that value is written into PDDR, it
does not affect the pin state. Table 22.8 summarizes port D data register read/write operations.
PDDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
• Bits 15 and 14— Reserved: These bits are always read as 0. The write value should always
be 0.
Rev. 3.0, 09/04, page 811 of 1086