SH7058 Datasheet, PDF (584/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
14
TST6
0
R/W 1: TEC/REC is writable with the same value at the
same time
13
TST5
0
R/W Forced Error Passive
Forces the HCAN to behave as an error passive
node, regardless of the error counters.
0: State of HCAN depends on error counters
1: HCAN behaves as an error passive node,
regardless of error counters
12
TST4
0
R/W Automatic Acknowledge Mode
Allows the HCAN to generate its own acknowledge
bit in order to enable the self test. In order to enter
self-test mode, the message transmitted needs to
be read back, and there are 2 settings for this. One
is to set (Enable Internal Loop = 1, Disable Tx
Output = 1, and Disable Rx Input = 1), so that the Tx
value is internally provided to the Rx. The other way
is to set (Enable Internal Loop = 0, Disable Tx
Output = 0, and Disable Rx Input = 0) and connect
the Tx and Rx onto the CAN bus so that the
transmitted data can be received via the CAN bus.
0: HCAN does not generate its own acknowledge bit
1: HCAN generates its own acknowledge bit
11
TST3
0
R/W Disable Error Counters
Enables/disables the error counters (TEC/REC).
When this bit is disabled, the error counters
(TEC/REC) remain unchanged and retain the
current value. When this bit is enabled, the error
counters (TEC/REC) operate according to the CAN
specification.
0: Error counters (TEC/REC) operate according to
the CAN specification
1: Error counters (TEC/REC) remain unchanged
and retain the current value
Rev. 3.0, 09/04, page 543 of 1086