SH7058 Datasheet, PDF (988/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bits 5 to 2—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit1— AUD Software Reset (AUDSRST): This bit controls AUD reset using software. Setting
AUDSRST bit to 1 places the AUD module in the power-on reset state.
Bit 1: AUDSRST Description
0
AUD reset state cleared
1
AUD reset state entered
(Initial value)
• Bit 0—RAME Enable (RAME): Selects enabling or disabling of the on-chip RAM. When
RAME is set to 1, on-chip RAM is enabled. When RAME is cleared to 0, on-chip RAM
cannot be accessed. In this case, a read or instruction fetch from on-chip RAM will return an
undefined value, and a write to on-chip RAM will be ignored. The initial value of RAME is 1.
When on-chip RAM is disabled by clearing RAME to 0, do not place an instruction that attempts
to access on-chip RAM immediately after the SYSCR1 write instruction, as normal access cannot
be guaranteed in this case.
When on-chip RAM is enabled by setting RAME to 1, place an SYSCR1 read instruction
immediately after the SYSCR1 write instruction. Normal access cannot be guaranteed if an on-
chip RAM access instruction is placed immediately after the SYSCR1 write instruction.
Bit 0: RAME
0
1
Description
On-chip RAM disabled
On-chip RAM enabled
(Initial value)
25.2.3 System Control Register 2 (SYSCR2)
Bit: 7
6
5
4
CKSEL
—
—
—
Initial value: 0
0
0
0
R/W: R/W
R
R
R
3
2
1
0
MSTOP3 MSTOP2 MSTOP1 MSTOP0
0
0
0
1
R/W
R/W
R/W
R/W
System control register 2 (SYSCR2) is an 8-bit readable/writable register that controls the standby
state of the AUD, H-UDI, FPU, and UBC on-chip modules.
SYSCR2 is initialized to H'01 by a power-on reset.
Note: The method of writing to SYSCR2 is different from that of ordinary registers to prevent
inadvertent rewriting. See section 25.2.4, Notes on Register Access, for more information.
• Bit 7—Internal Clock (φ) Select (CKSEL): See section 5, Clock Pulse Generator (CPG).
Rev. 3.0, 09/04, page 947 of 1086