SH7058 Datasheet, PDF (624/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

16.6.2 Timer Control Register_n (TCR_n) (n = 0, 1)
The timer control register (TCR) is a 16-bit readable/writable register that controls the operation
of the timer. This register should be set before each periodical transmission or the deadline
monitor register is set and the timer operation starts.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCR TCR TCR TCR TCR TCR TCR9
15 14 13 12 11 10
TCR7
TPSC TPSC TPSC TPSC TPSC TPSC
543210
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W  R/W  R/W R/W    
Bit
Bit Name Initial Value R/W Description
15
TCR15
0
R/W Enable Timer
When this bit is set, the timer runs. When this bit
is cleared, the timer completes the current cycle
(notified by timer overrun or a compare match
condition on TCMR0) and is cleared to 0.
0: Timer stops running and is cleared at the end
of current cycle
1: Timer is running
Important: There is a failure on the timer function
in the SH7058. This bit must be written to 0 not to
activate the timer.
14
TCR14
0
R/W Disable ICR0
Enables or disables the input capture register 0
(ICR0). When this bit is enabled, the timer value is
always captured every time a start of frame (SOF)
is output to the CAN bus, whether the HCAN is a
transmitter or receiver. When this bit is disabled,
the value of ICR0 remains latched.
0: ICR0 is disabled and holds the current value
Clearing condition:TCR9 = 1 when CAN-ID of
receive message is equal to the ID of a mailbox
with CCM set
1: ICR0 is enabled and captures the timer value at
every SOF
Rev. 3.0, 09/04, page 583 of 1086