SH7058 Datasheet, PDF (533/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 15.3 so that
the rising edge of the clock occurs at the center of each transmit data bit.
0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 frame
Figure 15.3 Output Clock and Communication Data Phase Relationship (Asynchronous
Mode)
Data Transmit/Receive Operation
SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE
bits to 0 in the serial control register (SCR), then initialize the SCI as follows.
When changing the operation mode or communication format, always clear the TE and RE bits to
0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the
transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER,
and ORER flags and receive data register (RDR), which retain their previous contents.
When an external clock is used, the clock should not be stopped during initialization or subsequent
operation. SCI operation becomes unreliable if the clock is stopped.
Rev. 3.0, 09/04, page 492 of 1086